Computers or other digital data processors that execute instructions often perform arithmetic operations on input operands to produce result operands, using a two's complement number format. High-performance arithmetic circuits, especially adders and subtractors, are important components in the design of such processors.
A given processor architecture may specify that two numbers are to be added together to produce specific results. For example, the architecture may specify two's complement encoded operands being added or subtracted to produce a two's complement result. Typically, there are multiple admissible implementations that perform the same architectural function. Some examples of admissible implementations of an adder that performs a particular arithmetic function may be a carry look ahead adder, a carry propagate adder, a carry skip adder or a carry save adder.
It is sometimes possible to incorporate different types of adders in different portions of the arithmetic circuit. An example may be an 8-bit carry propagate section followed by an 8-bit carry look ahead section that performs a 16-bit addition.
Additional details regarding these and other conventional aspects of digital data processor arithmetic can be found in, for example, B. Parhami, “Computer Arithmetic: Algorithms and Hardware Designs,” Oxford University Press, New York, 2000 (ISBN 0-19-512583-5), which is incorporated by reference herein.
Different arithmetic circuit implementations are developed to optimize various design parameters. Some important design parameters include propagation delay, area utilization, and power dissipation. Most adder implementations tend to trade off performance and area. Occasionally dynamic switching power, described in greater detail below, is considered in the design process.
Active power dissipation in circuit designs can be generally categorized as dynamic switching power and short circuit power. Dynamic switching power is dissipated when a transistor switches state (e.g., from 0->1 or 1->0). Short circuit power is transient in nature. It is manifest by either multiple transitions during switching due to skews between input signals or by transient state changes propagated by input signals that ultimately quiesce to a state that would not induce a transition.
A drawback of conventional arithmetic circuit implementations is that such implementations fail to adequately address the issues of dynamic switching power and short circuit power. This can lead to excessive power consumption, which is problematic in numerous digital data processor applications.
Accordingly, techniques are needed which can provide improved arithmetic circuitry performance, through reductions in dynamic switching power and short circuit power.